Wafer bonding enables the formation of non-standard material stacks that are becoming increasingly important for various high performance microelectronic device applications. As the semiconductor industry faces fundamental challenges in device scaling, there is more impetus to explore alternative materials and device structures, and the flexibility afforded by wafer bonding can potentially impact several promising new technologies.
For instance, three-dimensional (3D) integrated circuits (ICs) formed by wafer bonding will allow system designers greater possibilities for optimizing circuit performance and increasing circuit functionality; stacking different semiconductors (e.g., GaAs and Si) by wafer bonding facilitates the monolithic integration of optical and electronic devices; alternative substrates such as silicon-on-sapphire, which have high defect densities when formed by conventional heteroepitaxy, can be realized with much lower defect densities by wafer bonding and result in improved RF circuit performance; and the fabrication of novel device structures such as double-gate metal-oxide-semiconductor (DGMOS) transistors with improved performance and scalability can be aided by wafer bonding.
To achieve the requirements of the semiconductor industry for these various applications, the wafer bonding process must meet some stringent criteria. First and foremost, the bonding process must be compatible with established silicon processing, which precludes the introduction of non-standard materials and, in many cases, restricts allowable process temperatures. In addition, the wafer bonding process should exhibit: defect-free bonded interfaces, high bond strength, and scalability to large sample sizes (i.e., 200-300 mm diameter wafers). Finally, the bonding process reliability must be high to gain acceptance in manufacturing.
Wafer bonding has become virtually standard in silicon-on-insulator (SOI) substrate preparation and is used extensively for micro-electromechanical system (MEMS) device fabrication applications that tolerate high temperature processing (often greater than 1000° C.). However, many microelectronic device applications of wafer bonding (such as those in which dopant diffusion needs to be minimized, where back-end materials such as metals and low-k dielectrics are already part of the material stack, and where the wafer stack contains materials with large differences in their coefficients of thermal expansion) require that process temperatures be maintained at or below 400° C. Thus, the requirement of a low temperature bonding process that results in void and bubble free bonding interfaces with a high surface energy is crucial to realizing the full potential of wafer bonding for microelectronic applications.
Wafer bonding performed at low temperatures, however, results in bonded interfaces with low surface energies. This is a significant drawback, limiting the kinds of processing that can be performed subsequent to bonding. There have been several reports in the literature that suggest that the surface energy for low temperature bonding may be significantly enhanced by an oxygen plasma treatment of the wafer surfaces. Amirfeiz, et al. “Formation of silicon structures by plasma-activated wafer bonding”, J. Electrochem. Soc., 147 (7), 2693 (2000) have reported surface energies γ of approximately 1600 mJ/m2 for bonding of Si/Si and γ of approximately 900 mJ/m2 for bonding of SiO2/SiO2 following an O2 plasma surface treatment and storage at room temperature. However, Amirfeiz, et al. observed severe void formation at the interface after annealing.
Similarly, D. Pasquariello et al. “Oxidation and induced damage in oxygen plasma in-situ wafer bonding”, J. Electrochem. Soc., 147 (7), 2699 Nov. 1, 2002 (2000) have achieved fairly high surface energies γ of approximately 1400 mJ/m2 for direct bonding between Si wafers following O2 plasma treatment for temperatures as low as 200° C. However, the bonded interfaces displayed voids. Thus, while plasma treatments of the wafer surfaces prior to bonding yield high surface energies for low anneal temperatures (less than 400° C.), void formation at the interfaces still appears to be a problem. Void free bonding interfaces have been demonstrated at low temperatures using wet chemical pre-treatments of the bonding surfaces, however these techniques tend to have lower surface energies, typically less than 1400 mJ/m2.
In view of the drawbacks mentioned hereinabove with prior bonding processes, there is a need for providing a low temperature process for the direct bonding of wafers where the resultant bonded structure has high surface energies and contains bonding interfaces that have low defect density.